Customarily in EEPROM memory devices, a memory cell includes a state transistor intended to store an item of information. The state transistor includes a control gate and a floating gate, in series with an access transistor, or bit line selection transistor. The access transistor is controlled by a word line signal and makes it possible to access the state transistor electrically, in particular in order to read an item of data therefrom or write an item of data thereto.
Control gate selection transistors are connected between gate control lines and the control gates of the state transistors of a memory word. The control gate selection transistors are controlled by a dedicated control signal and make it possible to access the memory cells electrically, in particular in order to read an item of data therefrom or write an item of data thereto.
The voltages implemented in the course of data writes, generally including an erasure cycle and a programming cycle, must be high enough to inject or extract a charge of the floating gate of the state transistors through the Fowler-Nordheim effect.
However, the access transistors and control gate selection transistors intrinsically exhibit voltage limits beyond which they risk breakdowns, such as avalanches of the source-substrate or drain-substrate junctions, and premature wear.
These physical limits stem in particular from the densification of the arrangement of electronic components and the reduction in their sizes.
A consequence of the reduction in the size of components such as the access transistors and control gate selection transistors of integrated memory circuits is that they are no longer capable of transmitting the high voltages required for writing data.
Indeed, during an erasure cycle, high erasure voltages of 14V to 15V are applied to the control gates of the state transistors of the memory words. A memory word includes in a customary manner a group of memory cells, for example an octet or byte.
These high erasure voltages are transmitted through a control gate selection transistor having a breakdown voltage of its source-substrate or drain-substrate junction of the order of 12V.
During a programming cycle, high programming voltages of 14V to 15V are transmitted to the state transistor of a memory cell via the access transistor.
Likewise, the access transistors have a breakdown voltage of their source-substrate or drain-substrate junctions of the order of 12V.
The solutions involving maximizing the coupling factor of the floating gates and decreasing the tunnel oxide thickness reduce endurance and data retention performance, and have furthermore reached their technological limits (with coupling factors exceeding 80% and tunnel oxide thicknesses of less than 7 nm).
The solution involving increasing the write time is not effective and is opposed to the objectives of raising memory speeds.
The split voltage solution involves, briefly, applying combinations of negative and positive potentials so as to reach the high voltages required without however exceeding the breakdown voltages of the components.
That said, the split voltage technologies require in particular two charge pumps (one generating a negative potential and the other a positive potential), each using a substantial and relatively significant surface area at the periphery of the memory plane of the memory.
However, it is desirable to limit the use of the surface area of semiconductor substrates which support integrated circuits, thus the split voltage solution may be unsuitable, for example for low-density memories, comprising an already small memory plane which therefore cannot accept a large surface area at the periphery.